Mentor Graphics has built a tool that uses electronic descriptions of intellectual property (IP) cores and on-chip buses to automatically assemble simulations and firmware tests for system-on-chip (SoC) designs.
The company has taken advantage of the move towards platform-based, popularised by Palmchip, Philips, Tality and Toshiba among others.
The platform architectures use a common on-chip bus, such as ARM Holdings' Amba bus or IBM's CoreConnect, to link a processor with a set of preconfigured peripherals. This approach is designed to reduce the amount of time it takes to assemble the IP cores to build the guts of an application-specific SoC into which customer IP can be slotted.
Mentor's Platform Express combines IP core from its own portfolio with the cores from the semiconductor supplier or design house. The tool lets designers assemble a design using those cores. The resulting description then drives a set of software generators to build hardware description files and related program code.
John Wilson, platforms group business development manager of Mentor, said: "Most platform vendors provide a set of vertical-market peripherals. We provide IP that fits onto that platform. Platform Express will generate decode logic for the peripherals and, at the same time, create software, such as diagnostics, for them, as well as the verification environment."
To help it generate hardware descriptions for decode logic and diagnostics software, Wilson said the tool uses XML files. The XML tags annotate the design with information on bus modes that a particular core supports.
"The tool can seek out bridges from the IP library to hook up a core to a particular platform," said Wilson.
Most of the generators are written in Java and Wilson said that it should be possible to handle third-party generators.
To build diagnostics software, for example, the generic C source code that comes with a peripheral is tagged in an associated XML file that contains the names of functions and symbols that are associated with registers and other hardware elements. When the generator builds the decode logic, it uses that information to create an address map for the whole chip and to insert the relevant addresses into the source code.
Mentor will make Platform Express free to chip designers, although the verification environment it supports is based on the company's ModelSim, Seamless and Xray tools. The company is charging IP providers and semiconductor houses to port the tool to their platforms. The first to sign up for the programme are Altera, ARM, Denali and Oki Electric.
